Electromagnetic compatibility EMC/EMI has recently become vital for electronic and chip designers. This paradigm shift is primarily due to the ever increasing chip density and frequency as well as the low supply voltage. Paradoxically, the chip has literally become just like an antenna radiating a significant amount of electromagnetic energy, especially when a heatsink is present in the design. A typical device is an Intel Quad Core processor that has two cores in each die and two dies in the same package and, of course, a heatsink.
In this article, we show you how the duo HFWorks and SolidWorks are used to study the EMC aspects of an Intel Dual Die CPU around ISM radio bands, i.e. frequency of 2.05 GHz and 4.9 GHz. Electrical results such as return loss (S11), near- and far- and electromagnetic fields are  presented and compared to actual measurements. Thermal results including the temperature distribution and gradient are also presented with and without the heat sink.

 

Simulation of the Dual Die CPU

Figure 1 shows a transverse section of the studied Intel dual die processor with a heatsink along with its packaging structure, interconnects, and PCB infrastructure.   In this study, the complex internal interconnection of the chip is ignored and only a stripped version of the structure is considered, as shown in Figure 2, where the dual processor is modeled as a microstrip patch antenna with two coaxial feeds.  Indeed the stripped model is similar to the real structure of the chip.

The pins and interconnections in the actual integrated circuit are modeled as two coaxial feeds, as shown in Figures 1 and 2.  Consequently, the location of the feeds must be carefully designed because it pretty much shapes the overall performance of the assumed model. The dimensions and material properties used in the simulation are shown in Tables 1 and 2.  The Solidworks model of the structure and its surrounding air region is shown in Figure 3.  

Name	Typical (mm)
Height of Heatsink  HH	Variable
Height of IHS	1.65
Height of Die	1.15
Height of substrate	1.25
Depth of TIM	0.1
Depth of Die attach material	0.1
Depth of IHS Sealant	0.1
Length of Heatsink	67.5
Width of Heatsink	67.5
Length of Die	11.9
Width of Die	9.0
Length of substrate	37.5
Width of substrate	37.5
Length of IHS External	34
Width of IHS External	34
Length of IHS Internal	26
Width of IHS Internal	26

Name	Materials	Permittivity	Conductivity(Siemens/m)
Substrate	FR4 epoxy	4.4	0
Die	Silicon dioxide	4	0
IHS	Aluminum	1	3.8x107
Heatsink	Aluminum	1	3.8x107
TIM	Silicone	1.8	0
Die attach material	Silver	1	6.1x107
IHS Sealant	Epoxy	1.8	0

The antenna model of the CPU is excited via two circular wave ports with an impedance of .  The ports are located at the bottom of the substrate and connected to two copper coaxial feeds which come in contact with the IHS [1].

 

Figure 3 - 3D model of Intel Dual Die CPU processor with Heatsink

Simulation and results

A. Effects of the Heatsink

The simulation results are studied with and without the heatsink mounted upon the CPU model. Without heatsink, the resonant frequencies are found at 2.05 GHz with a reflection coefficient of -11.45 dB and 4.9 GHz -20.54 dB at port 1, and 2.05 GHz with a reflection coefficient -4.32 dB and 4.9 GHz with reflection coefficient -18.83 dB at port 2. When the heatsink is mounted upon the CPU, the resonant frequencies are found at 2.3 GHz with a reflection coefficient -25.83 dB and 5.45 GHz with a reflection coefficient -12.90 dB at port 1, and 2.3 GHz with a reflection coefficient -3.41 dB and 5.45 GHz with reflection coefficient -13.45 dB at port 2.   As shown in Figure 4, HFWorks results are close to measured data.  The far-field results at 2.05 GHz are depicted in Figure 5 and again show a good comparison with the measured data.

Figure 4 - (a) Reflection coefficient at port1. (b) Reflection coefficient at port2.

 

Figure 5 - (a)2D plot of radiation pattern at 2.05 GHz,  (b) 3D plot of radiation pattern at 2.05 GHz

 

B. Height of Heatsink

As shown in Figure 3, the heatsink is simplified as a solid block without fins. Different simulations were executed in order to study the effect of the height of the heatsink on the field and circuit results and to get the optimized structure of Dual die CPU with heatsink.  As shown in Table 1, the height of the heatsink has a minimal effect on the reflection coefficient at both port1 and port2.  Hence,  the resonant frequency and scattering parameters of the Intel dual die CPU depend heavily on its internal  structure and not on what is mounted upon it.

Simulation Setup  HFW (Port1)	Reflection coefficient
	GHz	dB
Height of Heatsink HH=37mm	1.75	-16.69169
	5.525	-6.11
Height of Heatsink HH=42mm	1.75	-16.74
	5.525	-6.09
Height of Heatsink HH=47mm	1.75	-25.28
	5.525	-11.21

Simulation Setup  HFW (port2)	Reflection coefficient
	GHz	dB
Height of Heatsink HH=37mm	1.75	-8.91
	5.525	-20.2224
Height of Heatsink HH=42mm	1.75	-11.38
	5.525	-13.10
Height of Heatsink HH=47mm	1.75	-11.42
	5.525	-12.25

 

C. Heat Simulation

Figure 6 shows the temperature distribution in the CPU due to the conductor and dielectric losses of the modeled structure.     
 

Conclusion

An Intel Dual Die CPU is simulated using the duo Solidworks and HFWorks and compared to measured data [1].   Various results show good agreement with measured results.

References

[1] Boyuan Zhu, Junwei Lu, and Erping Li, “Electromagnetic Compatibility Benchmark-Modeling Approach for a Dual-Die CPU”, IEEE Transactions on electromagnetic compatibility, February 2011, pp.91-98.