Advances in chip technology have escalated I/O densities and complex interconnects, demanding careful consideration of signal integrity in high-speed PCB designs to prevent data loss and system errors. This study on Flip-chip packages explores the impact of data rate, vias, and material losses on system performance.
HFWorks Modeling of Signal Integrity of High-Speed ICs
To contribute to this research effort, we took a flip-chip package design from a PhD thesis paper [1] and simulated it using our electromagnetic virtual prototyping software, HFWorks. To study the intricacies of signal integrity in high-speed ICs, we investigated three design issues which are mainly high density of interconnects, vias, and material properties.
Crosstalk
Today’s high-level functionality electronics stipulate the use of HDI PCBs that run on frequency of 10 GHz and higher. Boards have become more compact and tighter wiring density gives rise to the importance of crosstalk analysis.
Coupled Microstrip Lines
The coupled microstrip lines are simulated; the following results are obtained:
(a) Near-End (NEXT) and (b) Far-End Crosstalk (FEXT)
As illustrated in the two figures above, the near-end (NEXT)and far-end crosstalk (FEXT) are not major concerns at lower frequencies, however, they are considerably important factors at higher frequencies. By providing adequate spacing between traces, crosstalk noise is reduced. Therefore, it is crucial to consider a proper trace spacing in high-speed ICs to minimize signal distortion.
Vias
A via is one of the major discontinuities in high-speed ICs and can give rise to a reflection noise. The reflection noise increases time delay and produces overshoot, undershoot, and ringing.
A Package with Multiple Vias
(a) Insertion Loss and (b) Return Loss of a Package with Multiple Vias
We can notice from the above figure on the left that vias and anti-pads act as a low-pass filter for high-speed signals. Increasing the via diameter, i.e., decreasing the via-aspect ratio, has a little effect at lower frequencies and significant effect at higher frequencies. The via is one of the major impedance mismatches which can result in big reflections at high frequencies, as illustrated in the above figure on the right.
Substrate material
The electrical properties of dielectric materials used in packages and PCB can affect the electrical performance of digital interconnects. Using the right material helps reduce signal attenuation and maintain signal integrity of high-speed PCB.
Animation of Electric Field of a Package with Multiple Vias (10 GHz)
Insertion Loss for Different Substrate Materials
(a) Eye Diagram and (b) Bit Patterns of a TGV Package (10 Gbps)
(a) Eye Diagram and (b) Bit Patterns of a TSV Package (10 Gbps)
At frequencies up to 3GHz, there is almost no difference in the insertion loss between silicon, RO4350B and glass. However, as the frequency increases, the loss in silicon becomes significantly higher. In comparison between the dielectric materials, TGV (Through Glass Via) shows the best performance in terms of the insertion loss; hence, TGVs represent a promising technology for next generation 3D IC packaging and can take over the traditional TSV technology.
As per the eye diagram of the two receivers, the TSV attenuates the signal more than the TGV at 10 GHz. The same effect can be observed in the bit patterns of the receivers. Indeed, the silicon has more insertion loss than the glass at 10 GHz.
Conclusion
This research on high-speed ICs and Flip-chip packages has illuminated the intricate balance required to maintain signal integrity in the face of increasing interconnect density, via effects, and material properties. By utilizing HFWorks for electromagnetic virtual prototyping, we've identified viable strategies to mitigate crosstalk, optimize via configurations, and select substrate materials that minimize signal degradation. Our findings advocate for careful design consideration to enhance system reliability and performance in the evolving landscape of high-speed electronics.
Reference
[1] HYUNHO BAEK, 2013, “Signal and Power Integrity of High-Speed IC in Chip-Package System”
