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High Frequency Simulation of a Through-Silicon Via (TSV) for 3D Chip Using HFWorks for Solidworks Application


Three-dimensional interconnections with through-silicon-via (TSV) have been developed to increase bandwidth, reduce latency, and lower power consumption in modern chips. They serve the purpose of connecting different layers of a die-stack directly through the substrate. Typical dimensions of TSVs are in the range of 5 to 150 µm for the diameter and 20 to 200 µm for the via length. The utilization of TSVs enables an efficient interconnection technique, which leads to a more compact chip design and packaging compared to conventional wire bonding techniques as illustrated in Figure1.

Although 3D IC stacking has not been frequently used in memory and image sensors due to thermal and cost challenges, TSV based silicon interposers were employed by Xilinx to demonstrate 28 Gbps field-programmable gate array (FPGA) systems using a 2.5D architecture.

In this article, we will model and assess the performance of a through silicon via (TSV), by isolating a single TSV using the numerical simulator called HFWorks inside Solidworks.  A Through Silicon Via is designed with Solidworks and simulated using the S parameters analysis in HFWorks.

Design and simulation

Figure2, depicts the TSV connector designed with Solidworks. This application consists of TSV within a silicon-box surrounded by an air-box in the HFWorks environment. The silicon box has been chosen to have resistivity of 10?.cm. The implemented TSV is a copper bar 50?m in length with cross-section diameter of 5?m.

Wire connections comparison between 2D IC and 3D IC

Figure1 - Wire connections comparison between 2D IC and 3D IC.

It is covered with a layer of silicon dioxide with a 0.5?m thickness to insulate the TSV from the substrate. The top and bottom plates of the TSV are selected as wave port to apply the excitations with an impedance of 50 Ohm.

The 3D Solidworks model of the Through Silicon Via TSV

Figure2 - The 3D Solidworks model of the Through Silicon Via TSV.

The schematic diagram of the connector TSV is displayed in Figure3 and the geometrical parameters, materials used are summarized in Table1. 

 Schematic digaram of a single TSV.

Figure3 - Schematic digaram of a single TSV

Table1 - Dimensional details of the connector

Parameters Value Parts Materials
R 2.5 ?m TSV body Copper
dox 0.5 ?m Dielectric Silicon Dioxide
L 50 ?m Silicon box Silicon
    Air Box Air


The variations of the S parameter S11 is described in Figure4. As expected, it shows a minor insertion loss at high frequencies, this is mainly due to the existence of three fundamental modes inside the structure namely slow-wave mode, dielectric quasi-TEM mode, and skin-effect mode. The sharp slope indicates the transition from slow wave to quasi-TEM mode. 

Return loss S11 of the single TSV

Figure4 - Return loss S11 of the single TSV

The insertion loss S21 graph in Figure5 indicates that the input signal is attenuated by less than 0.00005 dB at 1GHz. This is a relatively a good result because we expect S21 to be close to 0.

Insertion loss S21 of the single TSV

Figure5 - Insertion loss S21 of the single TSV

The distribution of the electric field at 1 GHz is shown in Figure6. Clearly, the electric field is uniformly distributed along the fault free TSV within the substrate. 

Figure6 - Distribution of the electric field at 1GHz of the single TSV


This article presents the implemented 3D Through Silicon Via (TSV) structure in HFWorks for Solidworks. The insertion loss, return loss, and the distribution of the electric field were determined using the S-parameter study in HFWorks. The results obtained in HFWorks match the expected values as presented in References [1].


[1] Gong, Zheng, "TSV Equivalent Circuit Model using 3D Full-Wave Analysis" (2014). Electronic Theses and Dissertations. Paper 5238.